1. Field
Exemplary embodiments of the present invention relate to a delay circuit and, more particularly, to a technology for increasing accuracy of a delay circuit that operates based on a clock.
2. Description of the Related Art
A delay circuit refers to a circuit that delays input signals for a certain amount of time in order to adjust timing. Semiconductor devices often need to operate in synchronization with a variety of sequences and operation timings. Therefore, delay circuits are used in many semiconductor devices.
FIG. 1 illustrates a configuration of a conventional delay circuit that operates based on a clock.
Referring to FIG. 1, the delay circuit includes shift units S0 to S40. Each of the shift units S0 to S40 shifts a signal input thereto in synchronization with a clock CLK and outputs the shifted signal. Each of the shift units S0 to S40 may be a D flip-flop that operates in synchronization with a rising edge of the clock CLK.
The shift unit S0 at the head is used to synchronize an input signal INPUT with the clock CLK, and the remaining shift units S1 to S40 are used to sequentially delay signals synchronized by the shift unit S0. The delay circuit of FIG. 1 delays the input signal INPUT by 40 clocks, i.e., 40 periods of the clock CLK, and outputs the delayed signal as an output signal OUTPUT.
FIG. 2 illustrates a configuration of a conventional delay circuit using a frequency divided clock CLK2 having the same delay value as that of FIG. 1. The frequency divided clock CLK2 has a period twice that of the clock CLK of FIG. 1, and has a frequency that is half the frequency of the clock CLK of FIG. 1.
Referring to FIG. 2, the delay circuit includes shift units S0 to S20. Each of the shift units S0 to S20 shifts a signal input thereto by one clock cycle, in synchronization with a frequency divided clock CLK2, and outputs the shifted signal.
The shift unit S0 is used to synchronize an input signal INPUT with the frequency divided clock CLK2, and the remaining shift units S1 to S20 are used to sequentially delay respective signals synchronized by the shift unit S0. The delay circuit of FIG. 2 delays the input signal INPUT by 20 clock cycles, i.e., 20 periods of the frequency divided clock CLK2, and outputs the delayed signal as an output signal OUTPUT. One period of the frequency divided clock CLK2 is twice the period of the clock CLK of FIG. 1, and thus the delay circuit of FIG. 2 delays the input signal INPUT by 40 clock cycles, based on the clock CLK of FIG. 1.
That is, the delay circuit of FIG. 2 using the frequency divided clock CLK2 includes shift units S0 to S20, which are half the number of shifts units in the delay circuit of FIG. 1, but they have the same delay value as the delay circuit of FIG. 1.
FIG. 3 is a timing diagram illustrating operations of the delay circuit of FIG. 1 and the delay circuit of FIG. 2. Disadvantages of the delay circuit of FIG. 2 using the frequency divided clock CLK2 are described below with reference to FIG. 3.
Referring to FIG. 3, in CASE1, after the input signal INPUT is activated, the shift unit S0 synchronizes the input signal INPUT with an even cycle “e” of the clock CLK, i.e., an even-numbered activation. The delay circuit of FIG. 1 activates the output signal OUTPUT after 40 cycles of the clock CLK from when the input signal INPUT is synchronized with the even cycle “e”. Likewise, the delay circuit of FIG. 2 activates the output signal OUTPUT after 40 cycles of the clock CLK, i.e., after 20 cycles of the frequency divided clock CLK2, from when the input signal INPUT is synchronized with the even cycle “e”.
In CASE2, after the input signal INPUT is activated, the shift unit S0 of FIG. 1 synchronizes the input signal INPUT with an odd cycle “o” of the clock CLK, i.e., an odd-numbered activation, and the delay circuit of FIG. 1 activates the output signal OUTPUT after 40 cycles of the clock CLK from when the input signal INPUT is synchronized with the odd cycle “o”. In contrast, the delay circuit of FIG. 2 activates the output signal OUTPUT after 41 cycles of the clock CLK from when the input signal INPUT is synchronized with the odd cycle “o”. This is because the delay circuit of FIG. 2 operates in synchronization with the frequency divided clock CLK2, and thus the shift unit S0 of FIG. 2 synchronizes the input signal INPUT with an even cycle “e” of the clock CLK, and the delay circuit of FIG. 2 activates the output signal OUTPUT after 40 cycles of the clock CLK, i.e., after 20 cycles of the frequency divided clock CLK2, from when the input signal INPUT is synchronized with the even cycle “e”.
If a delay circuit is designed using the frequency divided clock CLK2 as described above, the area of the delay circuit may be reduced, but there is a concern in that the delay circuit does not have precise timing because the sampling and delay operations of the input signal INPUT are performed using the frequency divided clock CLK2.